SHIELD_DELAY=OFF, CSX_DUAL_CNT=ONE, IREF_SEL=IREF_SRSS, MUTUAL_CAP=SELFCAP, DSI_COUNT_SEL=CSD_RESULT, FULL_WAVE=HALFWAVE
Configuration and Control
| IREF_SEL | N/A 0 (IREF_SRSS): N/A 1 (IREF_PASS): N/A |
| FILTER_DELAY | Enables the digital filtering on the CSD comparator |
| SHIELD_DELAY | Configures the delay between shield clock and sensor clock 0 (OFF): Delay line is off; sensor clock = shield clock 1 (D5NS): shield clock is delayed by 5ns delay w.r.t sensor clock 2 (D10NS): shield clock is delayed by 10ns delay w.r.t sensor clock 3 (D20NS): shield clock is delayed by 20ns delay w.r.t sensor clock |
| SENSE_EN | Enables the sensor and shield clocks, CSD modulator output and turns on the IDAC compensation current as selected by CSD_IDAC. |
| FULL_WAVE | N/A 0 (HALFWAVE): Half Wave mode 1 (FULLWAVE): Full Wave mode |
| MUTUAL_CAP | N/A 0 (SELFCAP): Self-cap mode 1 (MUTUALCAP): Mutual-cap mode |
| CSX_DUAL_CNT | N/A 0 (ONE): N/A 1 (TWO): N/A |
| DSI_COUNT_SEL | N/A 0 (CSD_RESULT): N/A 1 (ADC_RESULT): N/A |
| DSI_SAMPLE_EN | DSI_SAMPLE_EN = 1 -> COUNTER will count the samples generated by DSI DSI_SAMPLE_EN = 0 -> COUNTER will count the samples generated by CSD modulator |
| SAMPLE_SYNC | N/A |
| DSI_SENSE_EN | DSI_SENSE_EN = 1-> sensor clock is driven directly by DSI DSI_SENSE_EN = 0-> sensor clock is driven by PRS/divide-by-2/DIRECT_CLOCK |
| LP_MODE | N/A |
| ENABLE | N/A |